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june 2009 doc id 15756 rev 1 1/24 24 STHDLS101A enhanced ac coupled hdmi level shifter with configurable hpd output features converts low-swing alternating current (ac) coupled differential input to high-definition multimedia interface (hdmi) rev 1.3 compliant hdmi level shifting operation up to 2.7 gbps per lane integrated 50 termination resistors for ac- coupled differential inputs input/output transition minimized differential signaling (tmds) enable/disable output slew rate control on tmds outputs to minimize electromagnetic interference (emi) and eliminate external components such as rc and choke fail safe outputs for backdrive protection no re-timing or configuration required inter-pair output skew < 250 ps, intra-pair output skew < 10 ps single power supply of 3.3 v esd protection: 6 kv hbm on all i/o pins integrated display data channel (ddc) level shifters. pass-gate volt age limiters allow 3.3 v termination on graphics and memory controller hub (gmch) pins and 5 v ddc termination on hdmi connector pins level shifter and configurable output for hpd signal from hdmi/dvi connector integrated pull-down resistor on hpd_sink and oe_n inputs applications notebooks, pc motherboards and graphic cards description the STHDLS101A is a high-speed high-definition multimedia interf ace (hdmi) level shifter that converts low-swing ac coupled differential input to hdmi 1.3 compliant open-drain current steering rx-terminated differential output. through the existing pci-e pins in the graphics and memory controller hub (gmch) of pcs or notebook motherboards, the pixel clock provides the required bandwidth (1.65 gbps, 2.25 gbps) for the video supporting 720p, 1080i, 1080p with a total of 36-bit resolution. the hdmi is multiplexed onto the pcie pins in the motherboard where the ac coupled hdmi at 1.2 v is output by gmch. the ac coupled hdmi is then level shifter by this device to 3.3 v dc coupled hdmi output. the STHDLS101A supports up to 2.7 gbps, which is enough for 12-bits of color depth per channel, as indicated in hdmi rev 1.3. the device operates from a single 3.3 v supply and is available in a 48-pin qfn package. qfn48 (7x7mm) table 1. device summary order code package packing STHDLS101Aqtr qfn48 (7 x 7 x 1 mm) tape and reel www.st.com
contents STHDLS101A 2/24 doc id 15756 rev 1 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 power supply and temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.2 differential inputs (in_d signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 tmds outputs (out_d signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 hpd input and output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 ddc input and output chatacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 oe_ input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6 hpd input resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7 esd performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STHDLS101A block diagram doc id 15756 rev 1 3/24 1 block diagram figure 1. STHDLS101A block diagram 50 10% in_d4+ in _d4- out_d4+ out_d4- 50 10% in_d 3 + in _d 3 - out_d 3 + out_d 3 - 50 10% in_d2+ in _d2- out_d2+ out_d2- 50 10% in_d1+ in _d1- out_d1+ out_d1- 10ma c u rrent driver 10ma c u rrent driver 10ma current driver 10ma c u rrent driver hpd_ s ource hpd_ s ink ddc_en s cl_ s ource s da_ s ource s cl_ s ink s da_ s ink oe_n rext 0 v 0v 0v 0v vcc 33 rx rx rx rx 160 k hpd level s hifter hpd
system interface STHDLS101A 4/24 doc id 15756 rev 1 2 system interface figure 2. system inferface figure 3. cable adapter 'raphicschipset '-#( onthe motherboard 0#) %xpress 3$6/ ($-) ($-)output connector !-6 34($,3! ,evelshifter $ongleor cable adapter $0 !-6 ($-)$6) 34($,3 !
STHDLS101A system interface doc id 15756 rev 1 5/24 figure 4. dp to hdmi/dvi cable adapter !-6 hdmi/dvi transmitter pc chipset hpd hpd_sink STHDLS101A hdmi/dvi cable adaptor ac_tmds dc tmds ddc ddc hdmi/dvi connector dp connector hpd_source ac_tmds ddc
pin configuration STHDLS101A 6/24 doc id 15756 rev 1 3 pin configuration figure 5. STHDLS101A pin configuration '.$ ).?$ ).?$ ).?$ /54?$ '.$ /54?$ /54?$ 3$!?3).+ (0$?3).+ ).?$ 6## 6## '.$ 1&. ).?$ ).?$ ).?$ &5.#4)/. &5.#4)/. 6## $$#?%. /54?$ 6## '.$ 3#,?3).+ '.$ 6## /54?$ '.$ '.$ '.$ 6## &5.#4)/. 6## '.$ 3$!?3/52#% &5.#4)/. 3#,?3/52#% 2%84 '.$ (0$?3/52#% !.!,/' /%?. ).?$ /54?$ 6## /54?$ /54?$ !-6
STHDLS101A pin configuration doc id 15756 rev 1 7/24 3.1 pin description table 2. pin description pin number name type function 1gnd powerground 2 vcc33 power 3.3 v10% dc supply 3 function1 vendor-specific control or test pins function pins are to enable vendor-specific features or test modes. for normal operation, these pins are tied to gnd or vcc33 for consistent interoperability, gnd is the preferred default connection for these signals. provides equalizer 6db lift at high frequencies 4 function2 vendor-specific control or test pins function pins are to enable vendor-specific features or test modes for normal operation, these pins are tied to gnd or vcc33 for consistent interoperability, gnd is the preferred default connection for these signals. provides 5 db equalizer gain at all frequencies 5gnd powerground 6 rext analog connection to external resistor. resistor value specified by device manufacturer. acceptable connections to this pin are: ? resistor to gnd ? resistor to 3.3 v ? nc (direct connections to v cc or gnd are through a 0 resistor for layout co mpatibility 7 hpd_source output buffer from the 0 v to 5 v input signal. the output buffer stage is configurable based on the function3 pin settings as desribed in the table below: function3 hpd_sink hpd_source 0low open-drain, connected an external pull up to the desired supply (normally 1 v) 0 high (5 v) low (0 v) 1 low (0 v) low (0 v) 1 high (5 v) high (3 v) 8 sda_source i/o 3.3 v ddc data i/o. pulled-up by external termination to 3.3 v. connected to sda_sink through voltage- limiting integrated nmos pass-gate
pin configuration STHDLS101A 8/24 doc id 15756 rev 1 9 scl_source input 3.3 v ddc clock i/o. pulled-up by external termination to 3.3 v. connected to scl_sink through voltage- limiting integrated nmos pass-gate 10 analog2 analog analog connection determined by vendor. acceptable connections to this pin are: ? resistor or capacitor to gnd ? resistor or capacitor to 3.3 v ? short to 3.3 v or to gnd ?nc 11 vcc33 power 3.3 v 10% dc supply 12 gnd power ground 13 out_d4+ output hdmi 1.3 compliant tmds output out_d4+ makes a differential output signal with out_d4- 14 out_d4- output hdmi 1.3 compliant tmds output out_d4- makes a differential output signal with out_d4+ 15 vcc33 power 3.3 v10% dc supply 16 out_d3+ output hdmi 1.3 compliant tmds output out_d3+ makes a differential output signal with out_d3- 17 out_d3- output hdmi 1.3 compliant tmds output out_d3- makes a differential output signal with out_d3+. 18 gnd power ground 19 out_d2+ output hdmi 1.3 compliant tmds output out_d2+ makes a differential output signal with out_d2-. 20 out_d2- output hdmi 1.3 compliant tmds output out_d2- makes a differential output signal with out_d2+ 21 vcc33 power 3.3 v10% dc supply 22 out_d1+ output hdmi 1.3 compliant tmds output. out_d1+ makes a differential output signal with out_d1- 23 out_d1- output hdmi 1.3 compliant tmds output. out_d1- makes a differential output signal with out_d1+ 24 gnd power ground table 2. pin description (continued) pin number name type function
STHDLS101A pin configuration doc id 15756 rev 1 9/24 25 oe_n input enable for level shifter path. 3.3 v tolerant low-voltage single-ended input. internal pull-down enables chip when unconnected oe_n in_d termination out_d outputs 1 high-z high-z 050 active 26 vcc33 power 3.3 v10% dc supply 27 gnd power ground 28 scl_sink output 5 v ddc clock i/o. pulled-up by external termination to 5 v. connected to scl_source through voltage- limiting integrated nmos pass-gate 29 sda_sink i/o 5v ddc data i/o. pulled-up by external termination to 5v. connected to sda_source through voltage- limiting integrated nmos pass-gate 30 hpd_sink input low-frequency, 0v to 5v (nominal) input signal. this signal comes from the hdmi connector. voltage high indicates ?plugged? state; voltage low indicates ?unplugged? state. hpd_sink is pulled down by an integrated 160k ? pull-down resistor 31 gnd power ground 32 ddc_en input enables bias voltage to the ddc pass-gate level shifter gates. (may be implemented as a bias voltage connection to the ddc pass-gate themselves) ddc_en pass-gate 0 v disabled 3.3 v enabled 33 vcc33 power 3.3 v10% dc supply 34 function3 input used for polarity control of the hpd_source output. when l, the hpd_source is an open-drain output sand when h, the hpd_source is a buffered output (o v to v cc ) 35 function4 vendor-specific control or test pins function pins are to enable vendor-specific features or test modes for normal operation, these pins are tied to gnd or vcc33 for consistent interoperability, gnd is the preferred default connection for these signals 36 gnd power ground 37 gnd power ground table 2. pin description (continued) pin number name type function
pin configuration STHDLS101A 10/24 doc id 15756 rev 1 38 in_d1- input low-swing differential input from gmch pcie outputs. in_d1- makes a differential pair with in_d1+ 39 in_d1+ input low-swing differential input from gmch pcie outputs. in_d1+ makes a differential pair with in_d1- 40 vcc33 power 3.3 v10% dc supply 41 in_d2- input low-swing differential input from gmch pcie outputs. in_d2- makes a differential pair with in_d2+ 42 in_d2+ input low-swing differential input from gmch pcie outputs. in_d2+ makes a differential pair with in_d2- 43 gnd power ground 44 in_d3- input low-swing differential input from gmch pcie outputs. in_d3- makes a differential pair with in_d3+ 45 in_d3+ input low-swing differential input from gmch pcie outputs. in_d3+ makes a differential pair with in_d3- 46 vcc33 power 3.3 v10% dc supply 47 in_d4- input low-swing differential input from gmch pcie outputs. in_d4- makes a differential pair with in_d4+ 48 in_d4+ input low-swing differential input from gmch pcie outputs. in_d4+ makes a differential pair with in_d4- table 2. pin description (continued) pin number name type function
STHDLS101A functional description doc id 15756 rev 1 11/24 4 functional description the section describes the basic functionality of the STHDLS101A device. power supply the STHDLS101A is powered by a single dc power supply of 3.3 v 10%. clocking this device does not retime any data. the device contains no state machines. no inputs or outputs of the device are latched or clocked. reset this device acts as a level sh ifter, reset is not required. oe_n function when oe_n is asserted (low level), the in_d and out_d signals are fully functional. input termina-tion resistors are enabled and any internal bias circuits are turned on. oe_n pin has an internal pull-down that enables the chip if left unconnected. when oe_n is de-asserted (high level), the out_d outputs are in high impedance state. the in_d input buffers are disabled and the in_d termination resistors are disabled. internal bias circuits for the differential inputs and outputs are turned off. power consumption of the chip is minimized. the hpd_sink input and hpd_source output are not affected by oe_n. the scl and sda pass-gates are not affected by oe_n. table 3. oe_n description oe_n device state comments asserted (low level) or unconnected differential input buffers and output buffers enabled. input impedance = 50 normal functioning state for in_d to out_d level shifting function. de-asserted (high level) low-power state. differential input buffers and terminations are disabled. differential input buffers are in high-impedance state. out_d level shifting outputs are disabled. out_d level shifting outputs are in a high-impedance state. internal bias currents are turned off. intended for lowest power condition when: ? no display is plugged in or ? the level shifted data path is disabled hpd_sink input and hpd_source output are not affected by oe_n. scl_source, scl_sink, sda_source and sda_sink signals and functions are not affected by oe_n.
functional description STHDLS101A 12/24 doc id 15756 rev 1 table 4. oe_n function oe_n in_dx out_dx (tmds outputs) notes de-asserted (high level) high-z high-z device disabled. low power state. internal bias currents are disabled. asserted or unconnected (low level) 50 termination enabled level shifting mode enabled.
STHDLS101A maximum ratings doc id 15756 rev 1 13/24 5 maximum ratings stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings symbol parameter value unit v cc supply voltage to ground potential -0.5 to +4.0 v v i dc input voltage (tmds and pcie ports) -0.5 to +4.0 v control pins -0.5 to +4.0 v sda_sink, scl_sink, hpd_sink pins -0.5 to +6 v i o dc output current 120 ma p d power dissipation 1 w t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c v esd electrostatic discharge voltage on ios (1) 1. in accordance with the mil standard 883 method 3015 human body model 6 kv table 6. thermal data symbol parameter qfn48 unit ja junction-ambient thermal coefficient 48 c/w
maximum ratings STHDLS101A 14/24 doc id 15756 rev 1 5.1 recommended operating conditions 5.1.1 power supply and temperature range 5.1.2 differential inputs (in_d signals) table 7. power supply and temperature range symbol parameter comments min typ max unit v cc33 3.3 v power supply 3.0 3.3 3.6 v i cc maximum power supply current total current from v cc 3.3 v power supply ?? 120 ma t operating temperature range -40 ? 85 o c table 8. differential input characteristics for in_d signals symbol parameter comments min typ max unit tbit unit interval tbit is determined by the display mode. nominal bit rate ranges from 250 mbps to 2.5 gbps per lane. nominal tbit at 2.5 gbps = 400 ps. 360 ps = 400 ps ? 10% 360 ?? ps v rx-diffp-p differential input peak to peak voltage v rx-diffp-p =2*|v rx-d+ - v rx- d- |. applies to in_d signals. 0.2 ? 1.2 v t rx-eye minimum eye width at in_d input pair the level shifter may add a maximum of 0.02ui jitter 0.8 ?? tbit v cm-ac-pp ac peak common mode input voltage vcm-ac-pp=|vrx-d+ + vrx-d-|/2 ? vrx-cm-dc. vrx-cm-dc=dc(avg) of |vrx-d+ + vrx-d-|/2 vcm-ac-pp includes all frequencies above 30 khz. ?? 100 mv z rx-dc dc single-ended input impedance applies to in_d+ as well as in_d- pins (50 ? 20% tolerance) 40 50 60 v rx-bias rx input termination voltage intended to limit power-up stress on chipset?s pcie output buffers 0 ? 2v z rx-high-z single-ended input resistance for in_dx when inputs are in high-z state differential inputs must be in a high impedance state 100 ?? k
STHDLS101A maximum ratings doc id 15756 rev 1 15/24 5.2 tmds outputs (out_d signals) the level shifter?s tmds out puts are required to meet the hdmi 1.3 specifications. the hdmi 1.3 specification is assumed to be the correct reference in instances where this document conflicts with t he hdmi 1.3 specification. table 9. differential output characteristics for tmds out_d signals symbol parameter comments min typ max unit v h single-ended high level output voltage av cc is the dc termination voltage in the hdmi or dvi sink. av cc is nominally 3.3 v av cc -10 mv av cc av cc +10 m v v v l single-ended low level output voltage the open-drain output pulls down form av cc av cc - 600 mv av cc - 500 mv av cc - 400 mv v v swing single-ended output swing voltage swing down from tmds termination voltage (3.3 v 10%) 400 mv 500 mv 600 mv v i off single-ended current in high-z state measured with tmds outputs pulled up to av cc max (3.6 v) through 50 ? resistors ?? 10 a t r rise time maximum rise/fall time at 2.7 gbps = 148ps. 125ps = 148 ? 15% 125 ps ? 0.4 tbit ps t f fall time maximum rise/fall time at 2.7 gbps = 148 ps. 125ps = 148 ? 15% 125 ps ? 0.4 tbit ps t skew- intra intra-pair differential skew this differential skew budget is in addition to the skew presented between d+ and d- paired input pins. ?? 10 ps t skew- inter inter-pair lane to lane output skew this lane to lane skew budget is in addition to the skew between differential input pairs. ?? 250 ps t jit jitter added to tmds signals jitter budget for tmds signals as they pass through the level shifter. 7.4 ps = 0.02 tbit at 2.7 gbps ?? 7.4 ps
maximum ratings STHDLS101A 16/24 doc id 15756 rev 1 5.3 hpd input and output characteristics table 10. hpd_sink input and hps_source output symbol parameter comment min typ max unit v ih-hpd_sink hpd_sink input high level low speed input changes state on cable plug/unplug 25.05.3v v il-hpd_sink hpd_sink input low level 0 ? 0.8 v i in-hpd_sink hpd_sink input leakage current measured with hpd_sink at v ih-hpd max and v il- hpd min ?? 50 a v ol- hpd_source hpd_source output low level when function3 = h v cc = 3.3 v 10% 2.5 ? v cc v v oh- hpd_source (inv) hpd_source output high level when function3 = l v cc = 3.3 v 10% i ol =1ma 0 ? 0.2 v v ol- hpd_source hpd_source output low level when function3 = h v cc = 3.3 v 10% 0 ? 0.2 v t hpd hpd_sink to hpd_source propagation delay time from hpd_sink changing state to hpd_source changing state. includes hpd_source rise/fall time c l =10 pf ?? 200 ns t rf-hpd hpd_source rise/fall time time required to transition from v oh-hpd_source to v ol-hpd_source or from v ol-hpd_source to v oh- hpd_source c l =10 pf 1 ? 20 ns
STHDLS101A maximum ratings doc id 15756 rev 1 17/24 5.4 ddc input and output chatacteristics table 11. sda_source, scl_source and sda_sink, scl_sink characteristics symb ol parameter comment min typ max unit v i input voltage on sda_sink, scl_sink pins voltage on the ddc pins on connector end 0 ? 5.5 v i lkg input leakage current on sda_sink, scl_sink pins v cc =3.3v v i =0.1v dd to 0.9 v dd to isolated ddc inputs v dd = external pull-up resistor voltage on sda_sink and scl_sink inputs (maximum of 5.5 v) -10 ? 10 a i off power-down leakage current on sda_sink, scl_sink pins v cc =0.0v v i = 0.1 v dd to 0.9 v dd to ddc sink inputs v dd = external pull-up resistor voltage on sda_sink and scl_sink inputs (maximum of 5.5 v) sda_source, scl_source = 0.0 v -10 ? 10 a c i/o input/output capacitance (switch off) v i(pp) =1 v, 100 khz v cc =3.3 v, t=25c ? 5 ? pf c i/o input/output capacitance (switch on) v i(pp) =1 v, 100khz v cc = 3.3 v, t= 25 c ?? 10 pf r on switch resistance i o =3 ma, v o =0.4v v cc =3.3v ? 27 40 t pd ddc_sink to ddc_source propagation delay time from ddc_sink changing state to ddc_source changing state while the pass gate is enabled. c l =10 pf r pu =1.5 k (min), 2.0 k (max) ? 815ns t sx switch time from ddc_en to the valid state on ddc_source c l =10pf r pu = 1.5 k (min), 2.0 k (max) ? 815ns
maximum ratings STHDLS101A 18/24 doc id 15756 rev 1 5.5 oe_ input characteristics 5.6 hpd input resistor 5.7 esd performance table 12. oe_n input characteristics symbol parameter comment min typ max unit v ih-oe_n input high level 2 ? vcc33 v v il-oe_n input low level 0 ? 0.8 v i in-oe_n input leakage current measured with oe_n at vih-oe_n max and vil- oe_n min ?? 200 a table 13. hdp input resistor symbol parameter comment min typ max unit r hpd hpd_sink input pull-down resistor guarantees hpd_sink is low when no display is plugged in 130 k 160 k 190 k table 14. esd performance symbol parameter test condition min typ max unit esd mil std 883 method 3015 (all pins) human body model (hbm) -6 ? +6 kv
STHDLS101A application information doc id 15756 rev 1 19/24 6 application information 6.1 power supply sequencing proper power-supply sequencing is ad vised for all cmos devices. it is recommended to always apply v cc before applying any signals to the input/output or control pins. 6.2 supply bypassing bypass each of the v cc pins with 0.1 f and 1nf capacitors in parallel as close to the device as possible, with the smaller-valued capacitor as close to the v cc pin of the device as possible. 6.3 differential traces the high-speed inputs and tmds outputs are the most critical parts for the device. there are several considerations to minimize discon tinuities on these transmission lines between the connectors and the device. ( a) maintain 100 differential transmission line impedance into and out of the device. (b) keep an uninterrupted ground plane below the high-speed i/os. (c) keep the ground-path vias to the device as close as possible to allow the shortest return current path. (d) layout of the tmds differential outputs should be with the shortest stubs from the connectors. output trace characteristics affect the per formance of the STHDLS101A. use controlled impedance traces to match trace impedance to both the transmission medium impedance and termination resistor. run the differential traces close together to minimize the effects of the noise. reduce skew by matching the electrical length of the traces. avoid discontinuities in the differential trace layout. avoid 90 degree turns and minimize the number of vias to further prevent impedance discontinuities.
package mechanical data STHDLS101A 20/24 doc id 15756 rev 1 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 6. package outline for qfn48 (7x7x 1 mm) - 0.5 mm pitch
STHDLS101A package mechanical data doc id 15756 rev 1 21/24 figure 7. tape information for qfn48 (7 x 7 x 1 mm) - 0.5 mm pitch table 15. package mechanical data for qfn48 (7 x 7 x 1 mm) - 0.5 mm pitch symbol min typ max min typ max a 0.80 0.90 1.00 0.80 0.85 1.00 a1 ? 0.02 0.05 ? 0.01 0.05 a2 ? 0.65 1.00 ? 0.65 ? a3 ? 0.25 ?? 0.20 ? b 0.18 0.23 0.30 0.18 0.23 0.30 d 6.85 7.00 7.15 6.90 7.00 7.10 d2 2.25 4.70 5.25 see exposed pad variations e 6.85 7.00 7.15 6.90 7.00 7.10 e2 2.25 4.70 5.25 see exposed pad variations e 0.45 0.50 0.55 0.45 0.50 0.55 l 0.30 0.40 0.50 0.30 0.40 0.50 ddd ?? 0.08 ?? 0.08
package mechanical data STHDLS101A 22/24 doc id 15756 rev 1 figure 8. reel information for qfn48 (7 x 7 x 1 mm) - 0.5 mm pitch table 16. reel mechanical data (dimensions in mm) acnt 330.2 13 0.25 100 16.4 00 8 4694_j
STHDLS101A revision history doc id 15756 rev 1 23/24 8 revision history table 17. document revision history date revision changes 22-jun-2009 1 initial release.
STHDLS101A 24/24 doc id 15756 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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